The present inventions relate generally to the electrical, electronic and computer arts and, more particularly, to nFET and pFET structures including stress-inducing features and the fabrication of such structures.
Fin-type field-effect transistors (FinFETs) have three-dimensional, non-planar configurations including fin-like structures extending above substrates. The substrates may include semiconductor on insulator (SOI) substrates or bulk semiconductor substrates. Semiconductor fins are formed in some FinFETs on substrates via known technology such as sidewall image transfer (SIT). FinFET structures including SOI substrates can be formed, in part, by selectively etching the crystalline silicon or other semiconductor layers down to the oxide or other insulating layers thereof following photolithography. Active fin heights, the channel fin region where the flow of electrical current is controlled by the gate, are set by SOI thickness when employing SOI substrates. In bulk FinFETs, active fin height is set by doping bottom portion of fins and the depth of gate wrap around. The gates of FinFETs can be formed using a “gate-first” process wherein a gate stack and spacers are formed prior to selective epitaxial growth wherein source and drain regions are enlarged. A “gate-last” process may alternatively be employed wherein a permanent gate stack is formed after forming source and drain regions. Gate-last procedures can involve forming a dummy gate, fabricating other elements of the transistor such as the source/drain regions, removing the dummy gate, and replacing the removed dummy gate with actual gate materials.